The present invention relates to microelectronic relays, and more specifically relates to a novel miniaturized microelectronic relay which can be economically and reliably manufactured.
Microelectronic relays are frequently contained within small outline packages (SOPs), such as those used in PCMCIA applications. Generally, such packages must be less than approximately 2 mm in thickness and must also meet certain regulatory safety standards. These safety requirements include maintenance of a dielectric isolation between the SOP""s input and output pins, and a pin arrangement allowing for minimum creepage distance. In miniature SOPs (for example, a six pin SOP-6 package), meeting such requirements becomes an especially critical issue.
Generally, this type of microelectronic relay contains a light-emitting diode (LED) at its input, and a photovoltaic generator (PVG) and field-effect transistors (FETs) at its output. When the LED is energized, photons from the LED impinge on the PVG and the latter generates sufficient gate current to trigger the FET and turn the relay on. When the LED does not receive any illumination, the PVG does not generate any current, and the FET, and thus the relay, is switched off. Thus, the relay switches on and off while maintaining complete isolation between its input and output since the input and output are coupled only by the output light of the LED.
One known microelectronic relay consists of an LED at the input and a PVG and one or more FETs at the output in which all parts are on a common plane. An optically clear medium couples the LED and PVG to maintain input/output voltage and current isolation. A single leadframe serves as the sole plane upon which a plurality of sets of relay elements are positioned. The LED is optically coupled to its respective PVG by reflection from the boundary of the optically clear medium. The PVG and FETs are wirebonded before encapsulization to form the desired control and output electrical circuits, and the leadframe and bonded wiring is then over molded. The assembled leadframe is then singulated to form the individual SOP packages. These packages, however, must be large enough in area to accommodate the three lateral coplanar chips.
Another known relay packaging technique uses two lead frames in spaced parallel planes for the coupling between LED, PVG and FETs. An input LED lies on a top plane (top and bottom are arbitrarily selected) with the LED positioned upside down. The output PVG and FETs lie on a bottom plane, with both elements facing upwards and suitably connected together and to the leadframe. To manufacture these dual plane devices, the lead frames must be upset and downset respectively to a proper dimension to meet the required regulatory isolation between input and output terminals. This design is hard to manufacture due to the inherent difficulty in accurately aligning each of the LED and PVG sets within the two lead frames relative to one another and does not produce in-line output pins on opposite sides of the chip.
The microelectronic relay of the invention and its method of manufacture presents a solution to the problem of the simplified proper alignment of the LED with the PVG during the construction of a relay while maintaining a small area or xe2x80x9cfootprintxe2x80x9d for the singulated devices and in-line output pins at opposite surfaces of the device housing. In the present invention, the microelectronic relay is manufactured using a combination of two interlocked lead frames: an input leadframe for the LED and an output leadframe for the PVG and FETs. Prior to the combination of the two lead frames, the LED is mounted on and connected to appropriate leads on the input leadframe, and the PVG and FETs are fixed to and connected to appropriate leads on the output leadframe. All relay elements are mounted and electrically connected to their respective leadframe with a curable conductive epoxy, or by soldering, or the like. Wirebonds provide the electrical connections to the respective leadframe elements.
Next, an optically clear elastomer is applied to the PVG elements on the lead frame. The application of the optically clear medium may be carried out by means of a syringe needle. After application to the PVG, the optically clear medium may be partially cured so as to prevent excessive flow.
The two lead frames are then combined with the assistance of integral locating pins on the two lead frames. The input leadframe is then held atop the output leadframe, with the LEDs upside down. The output leadframe is held with the PVGs and FETs facing upwards. Tabs in the output leadframe align with and fold into notches in the input leadframe in order to automatically position the two lead frames with respect to one another with precision. The lead frames are also bent in a novel manner such that, when the two lead frames are combined, the rails of the lead frames lie in a common plane. The entire combination of the interlocked lead frames, however, forms a dual plane relay, with the PVGs and LEDs precisely aligned and separated.
The combined lead frames are held together in this interlocked position for the remainder of the steps in the manufacturing process. The optically clear medium is next suitably completely cured, and a conventional transfer molding operation forms the main insulation packaging for each microelectronic relay section of the extending lead frames. The housings are then singulated, forming the individual small outline packages with small footprint and exactly spaced and aligned LED and PVG.